About the role
The team verifies next-generation RISC-V CPU cores. The engineer develops verification strategies, builds test environments, and debugs failures. This role involves working closely with architects and designers to ensure the quality of complex processor designs.
Our summary of the posting; the original is on the Tenstorrent careers page.
What the posting requires
- Required
- SystemVerilog
- Testbench development
- Constrained-random testing
- Assertions
- Functional coverage
- Debug
- C++
- UVM
- RTL
- Preferred
- Pipelines
- Out-of-order execution
- Caches
- Load/store
- Branch prediction
- Instruction scheduling
These tags are our reading of the posting. They can miss something; the original posting is the reference.