About the role
The team develops advanced ASICs for the Starlink satellite internet system. The engineer defines micro-architectures, implements RTL designs in Verilog/System Verilog, and collaborates with verification and implementation teams. This role also involves silicon bring-up and validation to enhance network capabilities.
Our summary of the posting; the original is on the SpaceX careers page.
What the posting requires
- Required
- US citizenship
- Verilog
- Micro-architecture
- RTL
- Verification
- Timing constraints
- Physical implementation
- Silicon bring-up
- Integration
- Preferred
- Clock domain crossings
- AXI
- High speed
- Python
- EDA tools
- Power optimization
These tags are our reading of the posting. They can miss something; the original posting is the reference.