About the role
The team verifies the instruction fetch unit for next-generation RISC-V CPU cores. The engineer develops verification strategies, creates tests, and debugs failures to ensure the processor's front-end logic functions correctly across various workloads.
Our summary of the posting; the original is on the Tenstorrent careers page.
What the posting requires
- Required
- SystemVerilog
- Constrained-random testing
- Debugging
- C++
- UVM
- Assertions
- RTL
- Python
- Functional coverage
- Preferred
- CPU front-end
- Queues
- Dispatch
- Hands-on
- Problem solving
- Collaborative
These tags are our reading of the posting. They can miss something; the original posting is the reference.